This invention relates to integrated circuits and printed circuit boards, including electrically-programmable, read-only-memory (EPROM) arrays, and to a sub-circuit and method for indicating the results of internal tests on those integrated circuits.
Design-for-test methods allow extended testing of an integrated circuit or a printed circuit board. In order for the special test to be effective, an observer must be able to detect the results of the special test by reading the output of the special test circuitry.
An EPROM array is but one example of a circuit or device in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen wordline select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EPROM array may contain thousands of cells. The sources of each cell in a column are connected to a source-column line. The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline.
During cell programming, appropriate programming voltages applied to the selected control-gate wordline and drain bitline to create a high-current condition in the selected channel region, injecting channel-hot electrons and/or avalanche-breakdown electrons across the channel oxide to the floating gate.
To improve manufacturing yield, redundant columns and rows of memory cells are used to replace columns or rows with defective memory cells. The integrated memory circuit may include a set of links or fuses that are programmed to provide address information pertaining to the columns or rows with the defective memory cells. Address information in the set of links or fuses is compared with the incoming addresses, and input and output data are routed to the redundant rows or columns.
Chips manufactured with "closed" electrical links as elements to program redundant address data may be programmed by electrically opening selected links with high currents and/or electric fields or may be programmed by using a laser to "explode" the link. Chips that are manufactured with "opened"=0 electrical links between two layers may be programmed by causing the links to form resistive shorts.
For the first case, in which selected "closed" links are "opened" during programming, complete "opens" are not always formed. Marginally opened links (or fuses) can cause incorrect results at different operating conditions or sequences. Typically, these are screened or tested by some complex or some non-standard method. Often, a new screen test will have to be developed for each new device.
A circuit and method to test the resistance of the open state of a packaged integrated circuit in response to a special test is described in U.S. patent application Ser. No. 07/574,835, filed Aug. 30, 1990 and also assigned to Texas Instruments Incorporated. The circuit described in that Application requires some means for transmitting the internal test results to the external environment.
Previous methods for observing the results of special test modes have required forcing special output results on normal output pins or have required adding hidden output modes on input/output pins or pads. Creating special pads requires added chip area for the pad and for driver circuits. In general, adding a hidden output mode on an input/output pad also requires added chip area. In many cases, output driver capacitance is increased by the added circuitry, adversely affecting response time for all circuit operations. In addition, electrostatic discharge capability may be adversely affected by the added circuitry.
Consequently, there is a need for a circuit and method for observing the results of an internal test mode using existing output states. Use of existing output states would not require adding hidden output modes, would not increase the output driver capacitance, and would not adversely affect electrostatic discharge capability.
The capability to furnish electronic signatures in response to certain inputs is a standard feature on many integrated circuits, including EPROMs. Industry standards require that, during the electronic signature mode of operation, two data codes be available at the outputs of an integrated circuit, the two data codes depending on the state of the A0 input pin. The two data codes identify the manufacturer and device type of the integrated circuit, i.e.:
Manufacturer Code: (Inputs: A9=12V, A0=0V) Output Code=10010111 97 PA0 Device Code: (Inputs: A9=12V, A0=5V) Output Code=00110010 32